1. Field of the Invention
The present invention relates to a method for the control of wafer surface temperatures of wafers which carry integrated circuits. More particularly, the invention is directed to a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates employed in the fabrication of semiconductor devices.
2. Discussion of the Prior Art
Numerous publications in this technology address themselves in varying degrees of applicability to the problem of controlling wafer surface temperatures, for example, during the post exposure baking of integrated circuit-carrying wafers for semiconductor devices.
Maeda, U.S. Pat. No. 5,626,782 is directed to a post exposure baking apparatus for forming fine resist integrated circuit line patterns on semiconductor wafers. In particular, this patent provides a capability for an evaluation in the changes of linewidth, and calculation methods for the temperatures in order to obtain desired linewidths for the integrated circuits, and for this purpose incorporates a plurality of heating pins which are independently temperature-controlled.
Marchman, et al., U.S. Pat. No. 5,656,182 is directed to a process for fabricating a device wherein control is provided by a near-field imaging latent effect which is introduced into energy-sensitive resist material. This effects a control over resist process parameters, wherein one of the parameters relates to the post-exposure baking.
Hobbs, et al., U.S. Pat. No. 5,516,608 is directed to a method for controlling line dimensions formed in a photolithographic process. The method employed in this patent consist of in implementing a measurement of an exposed pattern during the pattern development, and enables a real-time in-line control over critical dimensions for positive-tone chemically implied photoresist systems.
Tani, et al., U.S. Pat. No. 5,252,435 discloses a method for forming a pattern of integrated circuits on a substrate such as a wafer or chip through the intermediary of a high contrast pattern formed by the use of a post-exposure baking step in photoresist processing.
Although all of the foregoing patents to varying degrees direct themselves to different aspects of providing a control over the precision in the size and width of the line pattern for the formed integrated circuits, and also over the control of the semiconductor wafer surface temperatures during the post exposure bake step, there is no disclosure of the unique inventive feedback control concept which may be employed with the use of the in situ surface temperature-adjustable or controllable hot plate, as described in commonly assigned co-pending application Ser. No. 09/361,451; now U.S. Pat. No. 6,100,506 issued Aug. 8, 2000, the disclosure of which is incorporated herein by reference.